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71M6545/71M6545H Data Sheet
5
5.1
FIRMWARE INTERFACE
I/O RAM Map –Functional Order
In Table 59 and Table 60 , unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a ‘U’.
Unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. Reserved bits are identified with
an ‘R’, and must always be written with a zero. Writing values other than zero to reserved bits may have undesirable side effects and must be
avoided. Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected
to the VBAT_RTC pin and the pin voltage is within specification.
The I/O RAM locations listed in Table 59 have sequential addresses to facilitate reading by the MPU (e.g., in order to verify their contents). These
I/O RAM locations are usually modified only at boot-up. The addresses shown in Table 59 are an alternative sequential address to the addresses
from Table 60 which are used throughout this document. For instance, EQU[2:0] can be accessed at I/O RAM 0x2000[7:5] or at I/O RAM
0x2106[7:5] .
Table 59: I/O RAM Map – Functional Order, Basic Configuration
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CE6
2000
EQU[2:0]
U
CHOP_E[1:0]
RTM_E
CE_E
CE5
CE4
2001
2002
U
SUM_SAMPS[7:0]
SUM_SAMPS[12:8]
CE3
CE2
CE1
2003
2004
2005
U
U
CE_LCTN[5:0]
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
CE0
2006
DIFF6_E
DIFF4_E
DIFF2_E
DIFF0_E
RFLY_DIS
FIR_LEN[1:0]
PLS_INV
RCE0
RTMUX
2007
2008
U
CHOPR[1:0]
RMT6_E
TMUXR4[2:0]
RMT4_E
RMT2_E
U
TMUXR6[2:0]
TMUXR2[2:0]
FOVRD
2009
U
U
R
U
U
U
U
U
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
200A
200B
200C
200D
200E
200F
MUX_DIV[3:0]
MUX9_SEL
MUX7_SEL
MUX5_SEL
MUX3_SEL
MUX1_SEL
MUX10_SEL
MUX8_SEL
MUX6_SEL
MUX4_SEL
MUX2_SEL
MUX0_SEL
TEMP
DIO_R5
DIO_R4
DIO_R3
2010
201B
201C
201D
R
U
U
U
TEMP_PWR
U
OSC_COMP
U
DIO_R11[2:0]
DIO_R9[2:0]
TEMP_BAT
U
U
U
U
U
TEMP_PER[2:0]
DIO_RPB[2:0]
DIO_R10[2:0]
DIO_R8[2:0]
82
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